50分急求AT89C52单片机电子琴汇编程序!!要求发出16个音!
kuaidi.ping-jia.net 作者:佚名 更新日期:2024-08-29
51单片机程序 电子琴音阶
--Designer:
--Module:
--Description:
--Simulator:MAX plusII 10.0.9/Window XP
--Date:
--Modify date:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity speaker is
Port ( clk1 : in std_logic;
tone1 : in integer range 0 to 2047; --音符选择参数值
spks : out std_logic); --驱动扬声器的音频信号
end speaker;
architecture Behavioral of speaker is
signal preclk:std_logic;
signal spk:std_logic;
begin
pulse1:process(clk1) --此进程对系统时钟分频
variable count:integer range 0 to 6;
begin
if clk1'event and clk1='1' then
count:=count+1;
if count<3 then
preclk<='1';
elsif count<6 then
preclk<='0';
else count:=0;
end if;
end if;
end process pulse1;
genspks:process(preclk,tone1) --此进程完成音符发声算法
variable count11:integer range 0 to 1024;
begin
if preclk'event and preclk='1' then
count11:=count11+1;
if count11=tone1 then
spk<=not spk;
count11:=0;
end if;
end if;
spks<=spk;
end process;
end Behavioral;
--File:speaker.vhd
--Designer:
--Module:
--Description:
--Simulator:MAX plusII 10.0.9/Window XP
--Date:
--Modify date:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity dianziqin is
Port ( clk : in std_logic;
index : in STD_LOGIC_VECTOR(7 DOWNTO 0); --音符选择参数值
high : out std_logic;
code :out std_LOGIC_VECTOR(3 DOWNTO 0);
spk:out std_logic); --驱动扬声器的音频信号
end dianziqin;
architecture Behavioral of dianziqin is
COMPONENT tone IS
PORT(index : in std_logic_vector(7 downto 0); --音符输入
code : out std_logic_vector(3 downto 0); --音符显示
tone0 : out integer range 0 to 2047; --音符选择参数
high: out std_logic);
END COMPONENT;
COMPONENT speaker IS
PORT( clk1 : in std_logic;
tone1 : in integer range 0 to 2047; --音符选择参数值
spks : out std_logic);
END COMPONENT;
signal a:integer range 0 to 2047;
begin
u1:tone PORT MAP(index=>index,code=>code,tone0=>a,high=>high);
u2:speaker port map(clk1=>clk,tone1=>a,spks=>spk);
end Behavioral;
--File:tone.vhd
--Designer:
--Module:
--Description:
--Simulator:MAX plusII 10.0.9/Window XP
--Date:
--Modify date:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tone is
Port ( index : in std_logic_vector(7 downto 0); --音符输入
code : out std_logic_vector(3 downto 0); --音符显示
tone0 : out integer range 0 to 2047; --音符选择参数
high: out std_logic); --高音信号
end tone;
architecture Behavioral of tone is
begin
search :process(index) --此进程完成音符到音符的分频系数译码,音符的显示,高低音阶
begin
case index is
when "00000001" => tone0<=956;code<="0001";high<='0';
when "00000010" => tone0<=851;code<="0010";high<='0';
when "00000100" => tone0<=758;code<="0011";high<='0';
when "00001000" => tone0<=716;code<="0100";high<='0';
when "00010000" => tone0<=638;code<="0101";high<='0';
when "00100000" => tone0<=568;code<="0110";high<='0';
when "01000000" => tone0<=506;code<="0111";high<='0';
when "10000000" => tone0<=478;code<="0001";high<='1';
when others => NULL;
end case;
end process;
end Behavioral;
coder
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY coder IS
PORT(din:IN STD_LOGIC_VECTOR(3 downto 0);
dout:OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END;
ARCHITECTURE bev OF coder IS
BEGIN
PROCESS(din)
BEGIN
CASE din(3 downto 0) IS
WHEN "0000"=> dout<="0111111";
WHEN "0001"=> dout<="0000110";
WHEN "0010"=> dout<="1011011";
WHEN "0011"=> dout<="1001111";
WHEN "0100"=> dout<="1100110";
WHEN "0101"=> dout<="1101101";
WHEN "0110"=> dout<="1111101";
WHEN "0111"=> dout<="0000111";
WHEN "1000"=> dout<="1111111";
WHEN "1001"=> dout<="1101111";
WHEN "1010"=> dout<="1110111";
WHEN "1011"=> dout<="1111100";
WHEN "1100"=> dout<="0111001";
WHEN "1101"=> dout<="1011110";
WHEN "1110"=> dout<="1111001";
WHEN "1111"=> dout<="1110001";
WHEN OTHERS=> NULL;
END CASE;
END PROCESS;
END;
Counter10
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY counter10 IS
PORT( clk:IN STD_LOGIC;
reset:IN STD_LOGIC;
din:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
dout:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
c:OUT STD_LOGIC);
END counter10;
ARCHITECTURE bev OF counter10 IS
SIGNAL count:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
dout<=count;
PROCESS(clk,reset,din)
BEGIN
IF reset='0' THEN
count<=din;
c<='0';
ELSIF rising_edge(clk) THEN
IF count="1001" THEN
count<="0000";
c<='1';
ELSE
count<=count+1;
c<='0';
END IF;
END IF;
END PROCESS;
END bev;
Counter24
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY counter24 IS
PORT( clk:IN STD_LOGIC;
reset:IN STD_LOGIC;
din:IN STD_LOGIC_VECTOR(5 DOWNTO 0);
dout:OUT STD_LOGIC_VECTOR(5 DOWNTO 0));
END counter24;
ARCHITECTURE bev OF counter24 IS
SIGNAL count:STD_LOGIC_VECTOR(5 DOWNTO 0);
BEGIN
dout<=count;
PROCESS(clk,reset,din)
BEGIN
IF reset='0' THEN
count<=din;
ELSIF rising_edge(clk) THEN
IF count(3 DOWNTO 0)="1001" THEN
count(3 DOWNTO 0)<="0000";
count(5 DOWNTO 4)<=count(5 DOWNTO 4)+1;
ELSE count(3 DOWNTO 0)<=count(3 DOWNTO 0)+1;
end if;
if count="100011" THEN count<="000000";
END IF;
END IF;
END PROCESS;
END bev;
Counter6
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY counter6 IS
PORT( clk:IN STD_LOGIC;
reset:IN STD_LOGIC;
din:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
dout:OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
c:OUT STD_LOGIC);
END counter6;
ARCHITECTURE bev OF counter6 IS
SIGNAL count:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
dout<=count;
PROCESS(clk,reset,din)
BEGIN
IF reset='0' THEN
count<=din;
c<='0';
ELSIF rising_edge(clk) THEN
IF count="101" THEN
count<="000";
c<='1';
ELSE
count<=count+1;
c<='0';
END IF;
END IF;
END PROCESS;
END bev;
Dclock
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY dclock IS
PORT(clk:IN STD_LOGIC;
reset:IN STD_LOGIC;
soutl:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
south:OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
moutl:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
mouth:OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
hout:OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
load:in STD_LOGIC;
sel:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
h:in std_logic_vector(2 downto 0);
l:in std_logic_vector(3 downto 0));
END dclock;
ARCHITECTURE bev OF dclock IS
COMPONENT fp40m IS
PORT(clk:IN STD_LOGIC;
fp:OUT STD_LOGIC);
END COMPONENT;
COMPONENT counter10 IS
PORT(clk:IN STD_LOGIC;
reset:IN STD_LOGIC;
din:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
dout:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
c:OUT STD_LOGIC);
END COMPONENT;
COMPONENT counter6 IS
PORT(clk:IN STD_LOGIC;
reset:IN STD_LOGIC;
din:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
dout:OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
c:OUT STD_LOGIC);
END COMPONENT ;
COMPONENT counter24 IS
PORT(clk:IN STD_LOGIC;
reset:IN STD_LOGIC;
din:IN STD_LOGIC_VECTOR(5 DOWNTO 0);
dout:OUT STD_LOGIC_VECTOR(5 DOWNTO 0));
END COMPONENT ;
SIGNAL c1,c2,c3,c4:STD_LOGIC;
SIGNAL doutsl,doutml:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL doutsh,doutmh:STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL douth:STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL rdoutsh,rdoutmh:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL rdouth:STD_LOGIC_VECTOR(7 DOWNTO 0);
signal s:std_logic_vector(2 downto 0);
BEGIN
s<=sel;
process(sel)
begin
if load='1' then
case s is
when "100"=> douth(5 downto 4)<=h(1 downto 0);
douth(3 downto 0)<=l(3 downto 0);
when "010"=> doutmh(2 downto 0)<=h(2 downto 0);
doutml(3 downto 0)<=l(3 downto 0);
when"001"=> doutsh(2 downto 0)<=h(2 downto 0);
doutsl(3 downto 0)<=l(3 downto 0);
when others=>null;
end case;
end if;
end process;
u1:counter10 PORT MAP(clk=>clk,reset=>reset,din=>doutsl,
dout=>soutl,c=>c1); --秒低位十进制计数
u2:counter6 PORT MAP(clk=>c1,reset=>reset,din=>doutsh(2 downto 0),
dout=>south(2 downto 0),c=>c2); --秒高位十进制计数
u3:counter10 PORT MAP(clk=>c2,reset=>reset,din=>doutml,
dout=>moutl,c=>c3); --分低位十进制计数
u4:counter6 PORT MAP(clk=>c3,reset=>reset,din=>doutmh(2 DOWNTO 0),
dout=>mouth(2 downto 0),c=>c4); --分高位十进制计数
u5:counter24 PORT MAP(clk=>c4,reset=>reset,din=>douth(5 DOWNTO 0),
dout=>hout); --时24进制计数
END bev;
Fm40m
LIBRARY IEEE;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY fp40m IS
PORT(clk:IN STD_LOGIC; --40Hz
fp:OUT STD_LOGIC);--1Hz
END fp40m;
ARCHITECTURE bev OF fp40m IS
BEGIN
PROCESS(clk)
VARIABLE cnt:INTEGER RANGE 0 TO 19;
BEGIN
IF clk'EVENT AND clk='1' THEN
cnt:=cnt+1;
IF cnt<=20 THEN
fp<='1';
ELSIF cnt<=40 THEN
fp<='0';
ELSE cnt:=0;
END IF;
END IF;
END PROCESS;
END bev;
冗余设计
自己好好学吧。。。。又不难
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这位朋友,我的建议是:如果自己真得想学好单片机,那就一定得自己多多开动脑筋,上网找高手直接要程序是不会有利于自身提高的,你懂我的意思吗?
要相信自己能够解决,再解决不了,可以向高手询问局部问题,但不要是全部,总得包含自己的思考。
还有,不要觉得看书完全没必要,看书上的程序也是在初学时很有必要的
--Designer:
--Module:
--Description:
--Simulator:MAX plusII 10.0.9/Window XP
--Date:
--Modify date:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity speaker is
Port ( clk1 : in std_logic;
tone1 : in integer range 0 to 2047; --音符选择参数值
spks : out std_logic); --驱动扬声器的音频信号
end speaker;
architecture Behavioral of speaker is
signal preclk:std_logic;
signal spk:std_logic;
begin
pulse1:process(clk1) --此进程对系统时钟分频
variable count:integer range 0 to 6;
begin
if clk1'event and clk1='1' then
count:=count+1;
if count<3 then
preclk<='1';
elsif count<6 then
preclk<='0';
else count:=0;
end if;
end if;
end process pulse1;
genspks:process(preclk,tone1) --此进程完成音符发声算法
variable count11:integer range 0 to 1024;
begin
if preclk'event and preclk='1' then
count11:=count11+1;
if count11=tone1 then
spk<=not spk;
count11:=0;
end if;
end if;
spks<=spk;
end process;
end Behavioral;
--File:speaker.vhd
--Designer:
--Module:
--Description:
--Simulator:MAX plusII 10.0.9/Window XP
--Date:
--Modify date:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity dianziqin is
Port ( clk : in std_logic;
index : in STD_LOGIC_VECTOR(7 DOWNTO 0); --音符选择参数值
high : out std_logic;
code :out std_LOGIC_VECTOR(3 DOWNTO 0);
spk:out std_logic); --驱动扬声器的音频信号
end dianziqin;
architecture Behavioral of dianziqin is
COMPONENT tone IS
PORT(index : in std_logic_vector(7 downto 0); --音符输入
code : out std_logic_vector(3 downto 0); --音符显示
tone0 : out integer range 0 to 2047; --音符选择参数
high: out std_logic);
END COMPONENT;
COMPONENT speaker IS
PORT( clk1 : in std_logic;
tone1 : in integer range 0 to 2047; --音符选择参数值
spks : out std_logic);
END COMPONENT;
signal a:integer range 0 to 2047;
begin
u1:tone PORT MAP(index=>index,code=>code,tone0=>a,high=>high);
u2:speaker port map(clk1=>clk,tone1=>a,spks=>spk);
end Behavioral;
--File:tone.vhd
--Designer:
--Module:
--Description:
--Simulator:MAX plusII 10.0.9/Window XP
--Date:
--Modify date:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tone is
Port ( index : in std_logic_vector(7 downto 0); --音符输入
code : out std_logic_vector(3 downto 0); --音符显示
tone0 : out integer range 0 to 2047; --音符选择参数
high: out std_logic); --高音信号
end tone;
architecture Behavioral of tone is
begin
search :process(index) --此进程完成音符到音符的分频系数译码,音符的显示,高低音阶
begin
case index is
when "00000001" => tone0<=956;code<="0001";high<='0';
when "00000010" => tone0<=851;code<="0010";high<='0';
when "00000100" => tone0<=758;code<="0011";high<='0';
when "00001000" => tone0<=716;code<="0100";high<='0';
when "00010000" => tone0<=638;code<="0101";high<='0';
when "00100000" => tone0<=568;code<="0110";high<='0';
when "01000000" => tone0<=506;code<="0111";high<='0';
when "10000000" => tone0<=478;code<="0001";high<='1';
when others => NULL;
end case;
end process;
end Behavioral;
coder
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY coder IS
PORT(din:IN STD_LOGIC_VECTOR(3 downto 0);
dout:OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END;
ARCHITECTURE bev OF coder IS
BEGIN
PROCESS(din)
BEGIN
CASE din(3 downto 0) IS
WHEN "0000"=> dout<="0111111";
WHEN "0001"=> dout<="0000110";
WHEN "0010"=> dout<="1011011";
WHEN "0011"=> dout<="1001111";
WHEN "0100"=> dout<="1100110";
WHEN "0101"=> dout<="1101101";
WHEN "0110"=> dout<="1111101";
WHEN "0111"=> dout<="0000111";
WHEN "1000"=> dout<="1111111";
WHEN "1001"=> dout<="1101111";
WHEN "1010"=> dout<="1110111";
WHEN "1011"=> dout<="1111100";
WHEN "1100"=> dout<="0111001";
WHEN "1101"=> dout<="1011110";
WHEN "1110"=> dout<="1111001";
WHEN "1111"=> dout<="1110001";
WHEN OTHERS=> NULL;
END CASE;
END PROCESS;
END;
Counter10
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY counter10 IS
PORT( clk:IN STD_LOGIC;
reset:IN STD_LOGIC;
din:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
dout:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
c:OUT STD_LOGIC);
END counter10;
ARCHITECTURE bev OF counter10 IS
SIGNAL count:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
dout<=count;
PROCESS(clk,reset,din)
BEGIN
IF reset='0' THEN
count<=din;
c<='0';
ELSIF rising_edge(clk) THEN
IF count="1001" THEN
count<="0000";
c<='1';
ELSE
count<=count+1;
c<='0';
END IF;
END IF;
END PROCESS;
END bev;
Counter24
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY counter24 IS
PORT( clk:IN STD_LOGIC;
reset:IN STD_LOGIC;
din:IN STD_LOGIC_VECTOR(5 DOWNTO 0);
dout:OUT STD_LOGIC_VECTOR(5 DOWNTO 0));
END counter24;
ARCHITECTURE bev OF counter24 IS
SIGNAL count:STD_LOGIC_VECTOR(5 DOWNTO 0);
BEGIN
dout<=count;
PROCESS(clk,reset,din)
BEGIN
IF reset='0' THEN
count<=din;
ELSIF rising_edge(clk) THEN
IF count(3 DOWNTO 0)="1001" THEN
count(3 DOWNTO 0)<="0000";
count(5 DOWNTO 4)<=count(5 DOWNTO 4)+1;
ELSE count(3 DOWNTO 0)<=count(3 DOWNTO 0)+1;
end if;
if count="100011" THEN count<="000000";
END IF;
END IF;
END PROCESS;
END bev;
Counter6
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY counter6 IS
PORT( clk:IN STD_LOGIC;
reset:IN STD_LOGIC;
din:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
dout:OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
c:OUT STD_LOGIC);
END counter6;
ARCHITECTURE bev OF counter6 IS
SIGNAL count:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
dout<=count;
PROCESS(clk,reset,din)
BEGIN
IF reset='0' THEN
count<=din;
c<='0';
ELSIF rising_edge(clk) THEN
IF count="101" THEN
count<="000";
c<='1';
ELSE
count<=count+1;
c<='0';
END IF;
END IF;
END PROCESS;
END bev;
Dclock
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY dclock IS
PORT(clk:IN STD_LOGIC;
reset:IN STD_LOGIC;
soutl:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
south:OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
moutl:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
mouth:OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
hout:OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
load:in STD_LOGIC;
sel:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
h:in std_logic_vector(2 downto 0);
l:in std_logic_vector(3 downto 0));
END dclock;
ARCHITECTURE bev OF dclock IS
COMPONENT fp40m IS
PORT(clk:IN STD_LOGIC;
fp:OUT STD_LOGIC);
END COMPONENT;
COMPONENT counter10 IS
PORT(clk:IN STD_LOGIC;
reset:IN STD_LOGIC;
din:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
dout:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
c:OUT STD_LOGIC);
END COMPONENT;
COMPONENT counter6 IS
PORT(clk:IN STD_LOGIC;
reset:IN STD_LOGIC;
din:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
dout:OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
c:OUT STD_LOGIC);
END COMPONENT ;
COMPONENT counter24 IS
PORT(clk:IN STD_LOGIC;
reset:IN STD_LOGIC;
din:IN STD_LOGIC_VECTOR(5 DOWNTO 0);
dout:OUT STD_LOGIC_VECTOR(5 DOWNTO 0));
END COMPONENT ;
SIGNAL c1,c2,c3,c4:STD_LOGIC;
SIGNAL doutsl,doutml:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL doutsh,doutmh:STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL douth:STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL rdoutsh,rdoutmh:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL rdouth:STD_LOGIC_VECTOR(7 DOWNTO 0);
signal s:std_logic_vector(2 downto 0);
BEGIN
s<=sel;
process(sel)
begin
if load='1' then
case s is
when "100"=> douth(5 downto 4)<=h(1 downto 0);
douth(3 downto 0)<=l(3 downto 0);
when "010"=> doutmh(2 downto 0)<=h(2 downto 0);
doutml(3 downto 0)<=l(3 downto 0);
when"001"=> doutsh(2 downto 0)<=h(2 downto 0);
doutsl(3 downto 0)<=l(3 downto 0);
when others=>null;
end case;
end if;
end process;
u1:counter10 PORT MAP(clk=>clk,reset=>reset,din=>doutsl,
dout=>soutl,c=>c1); --秒低位十进制计数
u2:counter6 PORT MAP(clk=>c1,reset=>reset,din=>doutsh(2 downto 0),
dout=>south(2 downto 0),c=>c2); --秒高位十进制计数
u3:counter10 PORT MAP(clk=>c2,reset=>reset,din=>doutml,
dout=>moutl,c=>c3); --分低位十进制计数
u4:counter6 PORT MAP(clk=>c3,reset=>reset,din=>doutmh(2 DOWNTO 0),
dout=>mouth(2 downto 0),c=>c4); --分高位十进制计数
u5:counter24 PORT MAP(clk=>c4,reset=>reset,din=>douth(5 DOWNTO 0),
dout=>hout); --时24进制计数
END bev;
Fm40m
LIBRARY IEEE;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY fp40m IS
PORT(clk:IN STD_LOGIC; --40Hz
fp:OUT STD_LOGIC);--1Hz
END fp40m;
ARCHITECTURE bev OF fp40m IS
BEGIN
PROCESS(clk)
VARIABLE cnt:INTEGER RANGE 0 TO 19;
BEGIN
IF clk'EVENT AND clk='1' THEN
cnt:=cnt+1;
IF cnt<=20 THEN
fp<='1';
ELSIF cnt<=40 THEN
fp<='0';
ELSE cnt:=0;
END IF;
END IF;
END PROCESS;
END bev;
冗余设计
自己好好学吧。。。。又不难
答:以STC89C52芯片来设计电子时钟,采用C语言进行编程,可以实现以下一些功能:年、月、日、小时、分、秒的显示、定时报警功能。本次设计的电子时钟系统由时钟电路,LCD显示电路,定时报警电路,按键调整电路四部分组成。51单片机通过软件编程,在LCD1602液晶屏上实现年、月、日、小时、分、秒的显示;通过三个按...
答:AT89C52是一款兼容MCS51指令系统的单片机,它具备一系列强大的功能特性,便于在各种应用中使用。首先,它的8kB Flash ROM支持反复擦写,次数超过1000次,为程序的持久存储提供了可靠保障。该芯片拥有32个双向I/O口,可以灵活地连接外部设备,提供丰富的输入输出能力。256x8位的内部RAM提供了足够的数据存储空...
答:AT89C52是一个低电压,高性能CMOS 8位单片机,片内含8k bytes的可反复擦写的Flash只读程序存储器和256 bytes的随机存取数据存储器(RAM),器件采用ATMEL公司的高密度、非易失性存储技术生产,兼容标准MCS-51指令系统,片内置通用8位中央处理器和Flash存储单元,AT89C52单片机在电子行业中有着广泛的应用。编辑本段主要功能特性...
答:1、按键可以调整当时时间 2、按键可以调节定时时间 3、定时时间到继电器吸合 8位数码管显示 时间格式格式 12-08-00 标示12点08分00秒 S1 用于小时 加1操作 S2 用于小时减1操作 S3 用于分钟 加1操作 S4 用于分钟减1操作 / /*--- 名称:普通时钟 -*/ include<reg52.h> //包含头文件,一...
答:mDelay(50);P2=0xfd;P0=tab1[sh];mDelay(60);P2=0xfb;P0=0xbf;P2=0xf7;P0=tab1[ml];mDelay(60);P2=0xef;P0=tab1[mh];mDelay(60);P2=0xdf;P0=0xbf;P2=0xbf;P0=tab1[hl];mDelay(60);P2=0x7f;P0=tab1[hh];mDelay(60);}} void t0() interrupt 1 using 1 { TH0=-...
答://先进行50ms预判断,若TH0计数值大于12,说明1S内计数值将超过65535(虽0.5S内远不超65535)//变量ee是无符号整数不能超过65535,为防止出错,则报警 //最大可测频率约65535hz,实际上STC12C系列是1T单片机,11.0592下其最高可计数频率远大于此 include <reg52.h> include <math.h> define uint...
答:如果电路都没有设计,可用按如下方式设计:32个LED正极分别用一个1K的电阻与VCC相连,每四个为一组,将负极并连;每组的负极分别接单片机P0口的一个IO脚。(如图)程序如下:main(){ int i,flag;P0=0xff;flag=0;while(1){ if(flag==0)flag=1;P0=~flag;flag<<=1;for(i=0;i<10000;i+...
答:能做到。用三个口,就可以轻松做到。见下图:
答:include <reg52.h> define uchar unsigned char define uint unsigned int define ulong unsigned long uchar code table[]="2000:01:01Week:W";// uchar code table1[]="T:00:00:00#00:00";sbit lcd_rs=P2^6;//定义LCD端口 sbit lcd_rw=P3^6;sbit lcd_en=P2^5;sbit k1=P3^2;/...
答:“第二输出功能线”与锁存器的输出端Q通过一个与非门和管脚部分连接。这样,如果“内部总线”向锁存器Q端输入1时,根据与非门的逻辑关系,与非门的输出端(即场效应管的栅极G)则反相跟随第二输出功能线的电平,此时,如果第二输出功能线为高电平,场效应管输入为低电平,于是场效应管截止,这样,...